1. Field of the Invention
The present invention relates to a multiport memory system which permits simultaneous, page-by-page accesses from a number of the same or different kinds of processors or disk systems (each including disk units and a disk controller).
2. Description of the Related Art
Conventional memory systems accessible from a plurality of processors cope with an access collision by means of time sharing or an arbiter.
When the time sharing technique is utilized, the number of processors allowed to concurrently access the memory is only several at the most, owing to limited memory access time. In the case of employing the arbiter, only one of the processors competing for access is given acknowledgement at a time and the others are forced to wait their turn. Accordingly, an increase in the number of processors involved in the access conflict will cause a marked increase in the waiting time of each processor for its turn.
As a solution to these problems, there has recently been introduced a multiport memory system which is adapted to be accessed page by page and allow the access thereto to start anywhere in the page so that it permits concurrent accesses from a number of processors without forcing them to wait their turn (Yuzuru Tanaka, "A Multiport Page-Memory Architecture and a Multiport Disk-Cache System", New Generation Computing, Vol. 2, No. 3, pp. 241-260, 1984).
However, the above article makes no reference to an addressing method. Moreover, the system is defective in that an increase in the number of processors increases the width of connection bus, introducing difficulty in packaging, and in that pipeline processing for making up for a delay resulting from the use of a multi-stage switching network is complex, raising the cost of the entire system.